PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
REFCLKA:
The SBI reference clock active bit (REFCLKA) monitors for low to high
transitions on the REFCLK input. REFCLKA is set high on a rising edge of
REFCLK, and is set low when this register is read.
FASTCLKA:
The SBI fast clock active bit (FASTCLKA) monitors for low to high transitions
on the FASTCLK input. FASTCLKA is set high on a rising edge of FASTCLK,
and is set low when this register is read.
C1FPA:
The SBI frame pulse active bit (C1FPA) monitors for low to high transitions on
the C1FP input. C1FPA is set high on a rising edge of C1FP, and is set low
when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
99
PMC [ PMC-SIERRA, INC ]
