PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
remains valid when interrupts are disabled and may be polled to detect TD
free queue error events.
IOCE:
The transmit interrupt on complete enable bit (IOCE) enables transmission
complete interrupts to the PCI host. When IOCE is set high, complete
transmission of a packet with the IOC bit in the TD set high will cause an
interrupt to be generated on the PCIINTB output. Interrupts are masked
when IOCE is set low. However, the IOCI bit remains valid when interrupts
are disabled and may be polled to detect transmission of IOC tagged
packets.
TFUDRE:
The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables
transmit FIFO underflow error interrupts to the PCI host. When TFUDRE is
set high, attempts to read data from the logical FIFO when it is already empty
will cause an interrupt to be generated on the PCIINTB output. Interrupts are
masked when TFUDRE is set low. However, the TFUDRI bit remains valid
when interrupts are disabled and may be polled to detect transmit FIFO
underflow events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
93
PMC [ PMC-SIERRA, INC ]
