RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x208 : RHDL Indirect Channel Data Register #2
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
7BIT
PRIORITY
INVERT
Unused
CRC[1]
CRC[0]
OFFSET[1]
OFFSET[0]
Unused
Unused
Unused
0
0
0
X
0
0
0
0
X
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
Bit 4
Bit 3
Bit 2
Bit 1
Unused
R/W
R/W
R/W
R/W
XFER[3]
XFER[2]
XFER[1]
XFER[0]
Bit 0
This register contains data read from the channel provision RAM after an indirect
read operation or data to be inserted into the channel provision RAM in an
indirect write operation.
XFER[3:0]:
The indirect channel transfer size (XFER[3:0]) configures the amount of data
transferred in each transaction. The channel transfer size to be written to the
channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. When the channel FIFO depth reaches
the depth specified by XFER[3:0] or when an end-of-packet exists in the
FIFO, a poll of this FREEDM-32A256 device will indicate that data exists and
is ready to be transferred across the receive APPI. Channel transfer size is
PROPRIETARY AND CONFIDENTIAL
108
PMC [ PMC-SIERRA, INC ]
