RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x204 : RHDL Indirect Channel Data Register #1
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R
W
W
W
W
W
W
W
W
W
W
W
W
PROV
STRIP
DELIN
0
0
0
TAVAIL
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved
FPTR[10]
FPTR[9]
FPTR[8]
FPTR[7]
FPTR[6]
FPTR[5]
FPTR[4]
FPTR[3]
FPTR[2]
FPTR[1]
FPTR[0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register contains data read from the channel provision RAM after an indirect
read operation or data to be inserted into the channel provision RAM in an
indirect write operation.
FPTR[10:0]:
The indirect FIFO block pointer (FPTR[10:0]) identifies one of the blocks of
the circular linked list in the partial packet buffer used in the logical FIFO of
the current channel. The FIFO pointer to be written to the channel provision
RAM, in an indirect write operation, must be set up in this register before
triggering the write. The FIFO pointer value can be any one of the blocks
provisioned to form the circular buffer.
PROPRIETARY AND CONFIDENTIAL
105
PMC [ PMC-SIERRA, INC ]
