RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
measured in 16 byte blocks. The amount of data transferred and the depth
threshold are specified by given setting is:
XFER[3:0] + 1 blocks = 16 * (XFER[3:0] + 1) bytes
XFER[3:0] should be set such that the number of blocks transferred is at least
two fewer than the total allocated to the associated channel. XFER[3:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
OFFSET[1:0]:
The packet byte offset (OFFSET[1:0]) configures the partial packet processor
to insert invalid bytes at the beginning of a packet stored in the channel FIFO.
The value of OFFSET[1:0] to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. The number of bytes inserted before the beginning of a
HDLC packet is defined by the binary value of OFFSET[1:0]. OFFSET[1:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
CRC[1:0]:
The CRC algorithm bits (CRC[1:0]) configures the HDLC processor to perform
CRC verification on the incoming data stream. The value of CRC[1:0] to be
written to the channel provision RAM, in an indirect channel write operation,
must be set up in this register before triggering the write. CRC[1:0] is ignored
when DELIN is low. CRC[1:0] reflects the value written until the completion of
a subsequent indirect channel read operation.
Table 11 – CRC[1:0] Settings
CRC[1]
CRC[0]
Operation
0
0
1
1
0
1
0
1
No Verification
CRC-CCITT
CRC-32
Reserved
INVERT:
The HDLC data inversion bit (INVERT) configures the HDLC processor to
logically invert the incoming HDLC stream from the RCAS256 before
PROPRIETARY AND CONFIDENTIAL
109
PMC [ PMC-SIERRA, INC ]
