RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
RMV8FPC
Type
Input
Pin
No.
P23
Function
The receive 8.192 Mbps H-MVIP frame
pulse clock signal (RMV8FPC) provides the
receive frame pulse clock for links
configured for operation in 8.192 Mbps H-
MVIP mode.
RMV8FPC is used to sample RFP8B.
RMV8FPC is nominally a 50% duty cycle,
clock with a frequency of 4.096 MHz. The
falling edge of RMV8FPC must be aligned
with the falling edge of RMV8DC with no
more than ±10 ns skew.
RMV8FPC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
RMV8DC
Input
R22
The receive 8.192 Mbps H-MVIP data clock
signal (RMV8DC) provides the receive data
clock for links configured to operate in 8.192
Mbps H-MVIP mode.
RMV8DC is used to sample data on RD[4m]
(0?m?7) when link 4m is configured for
8.192 Mbps H-MVIP operation. RMV8DC is
nominally a 50% duty cycle clock with a
frequency of 16.384 MHz.
RMV8DC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
RBD
Tristate
Output
R23
The receive BERT data signal (RBD)
contains the receive bit error rate test data.
RBD reports the data on the selected one of
the receive data signals (RD[31:0]) and is
updated on the falling edge of RBCLK.
RBD may be tristated by setting the RBEN
bit in the FREEDM-32A256 Master BERT
Control register low. BERT is not supported
for H-MVIP links.
PROPRIETARY AND CONFIDENTIAL
16
PMC [ PMC-SIERRA, INC ]
