RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Pin
No.
Function
RBCLK
Tristate
Output
R20
The receive BERT clock signal (RBCLK)
contains the receive bit error rate test clock.
RBCLK is a buffered version of the selected
one of the receive clock signals
(RCLK[31:0]). RBCLK may be tristated by
setting the RBEN bit in the FREEDM-
32A256 Master BERT Control register low.
BERT is not supported for H-MVIP links.
PROPRIETARY AND CONFIDENTIAL
17