RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
7
PIN DESCRIPTION
Table 1 – Line Side Interface Signals (154)
Pin Name
Type
Pin
No.
Function
RCLK[0]
Input
N23
N21
M22
L21
L20
K22
J22
The receive line clock signals (RCLK[31:0])
contain the recovered line clock for the 32
independently timed links. Processing of
the receive links are on a priority basis, in
descending order from RCLK[0] to
RCLK[1]
RCLK[2]
RCLK[3]
RCLK[4]
RCLK[5]
RCLK[31]. Therefore, the highest rate link
should be connected to RCLK[0] and the
lowest to RCLK[31].
RCLK[6]
RCLK[7]
J23
RCLK[8]
G21
G20
F22
F21
E21
D23
D21
C21
B22
A21
C20
A20
C19
C18
B18
D17
B16
A15
B15
A14
C14
A13
C13
B12
For channelised T1/J1 or E1 links, RCLK[n]
must be gapped during the framing bit (for
T1/J1 interfaces) or during time-slot 0 (for
E1 interfaces) of the RD[n] stream. The
FREEDM-32A256 uses the gapping
information to determine the time-slot
alignment in the receive stream.
RCLK[9]
RCLK[10]
RCLK[11]
RCLK[12]
RCLK[13]
RCLK[14]
RCLK[15]
RCLK[16]
RCLK[17]
RCLK[18]
RCLK[19]
RCLK[20]
RCLK[21]
RCLK[22]
RCLK[23]
RCLK[24]
RCLK[25]
RCLK[26]
RCLK[27]
RCLK[28]
RCLK[29]
RCLK[30]
RCLK[31]
RCLK[31:0] is nominally a 50% duty cycle
clock of frequency 1.544 MHz for T1/J1 links
and 2.048 MHz for E1 links.
For unchannelised links, RCLK[n] must be
externally gapped during the bits or time-
slots that are not part of the transmission
format payload (i.e. not part of the HDLC
packet). RCLK[2:0] is nominally a 50% duty
cycle clock between 0 and 51.84 MHz.
RCLK[31:3] is nominally a 50% duty cycle
clock between 0 and 10 MHz.
The RCLK[n] inputs are invalid and should
be forced to a low state when their
associated link is configured for operation in
H-MVIP mode.
PROPRIETARY AND CONFIDENTIAL
12
PMC [ PMC-SIERRA, INC ]
