RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
In the transmit direction, polling is done at the channel level. Polling is
completely decoupled from selection. To increase the polling bandwidth, up to
two channels may be polled simultaneously. The polling engine in the external
controller runs independently of other activity on the transmit APPI. In response
to a positive poll, the external controller may commence partial packet data
transfer across the transmit APPI for the successfully polled channel of a
FREEDM-32A256 device. The external controller must prepend an in-band
channel address to each partial packet transfer across the transmit APPI to
associate the data with a channel.
In the receive direction, the FREEDM-32A256 performs channel assignment and
packet extraction and validation. For each provisioned HDLC channel, the
FREEDM-32A256 delineates the packet boundaries using flag sequence
detection, and performs bit de-stuffing. Sharing of opening and closing flags, as
well as sharing of zeros between flags are supported. The resulting packet data
is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet
buffer acts as a logical FIFO for each of the assigned channels. An external
controller transfers partial packets out of the RAM, across the receive APPI bus,
into host packet memory. The FREEDM-32A256 validates the frame check
sequence for each packet, and verifies that the packet is an integral number of
octets in length and is within a programmable minimum and maximum lengths.
Receive APPI bus latency may cause one or more channels to overflow, in which
case, the packets are aborted. The FREEDM-32A256 reports the status of each
packet on the receive APPI at the end of each packet transfer.
Alternatively, in the receive direction, the FREEDM-32A256 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-32A256 directly transfers the received octets onto the receive APPI
verbatim. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the received time-slots.
In the transmit direction, an external controller provides packets to transmit using
the transmit APPI. For each provisioned HDLC channel, an external controller
transfers partial packets, across the transmit APPI, into the internal 32 Kbyte
transmit partial packet buffer. The partial packets are read out of the partial
packet buffer by the FREEDM-32A256 and a frame check sequence is optionally
calculated and inserted at the end of each packet. Bit stuffing is performed
before being assigned to a particular link. The flag or idle sequence is
automatically inserted when there is no packet data for a particular channel.
Sequential packets are optionally separated by a single flag (combined opening
and closing flag) or up to 128 flags. Zeros between flags are not shared in the
transmit direction although, as stated previously, they are accepted in the receive
direction. Transmit APPI bus latency may cause one or more channels to
PROPRIETARY AND CONFIDENTIAL
9
PMC [ PMC-SIERRA, INC ]
