RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
9.7.6 Free Queue Cache
The Free Queue Cache block implements the 6 element TDR Free Queue
cache. Caching TDRs reduces the number of host bus accesses that the
TMAC672 makes.
TDRs are written to the cache one at a time as they are released by the
TMAC672. The cache is then flushed to host memory when it becomes full,
when a TD with the IOC bit set high is released, when the FQFLUSH register bit
is set high or when a TD is released as the result of unprovisioning a channel.
The cache controller may also flush the cache when it contains fewer than six
elements or if the pointer index is within six elements of the end of the free
queue. When the write pointer is near the end of the free queue, the cache
controller writes only to the end of the queue and does not start writing from the
top of the queue until the next time a flush is required. To do so would require
two host memory transactions and would be of no benefit.
9.8 Transmit HDLC Controller / Partial Packet Buffer
The Transmit HDLC Controller / Partial Packet Buffer block (THDL672) contains
a partial packet buffer for PCI latency control and a transmit HDLC controller.
Packet data retrieved from the PCI host memory by the Transmit DMA Controller
block (TMAC672) is stored in channel specific FIFOs residing in the partial
packet buffer. When the amount of data in a FIFO reaches a programmable
threshold, the HDLC controller is enabled to initiate transmission. The HDLC
controller performs flag generation, bit stuffing and, optionally, frame check
sequence (FCS) insertion. The FCS is software selectable to be CRC-CCITT or
CRC-32. The minimum packet size, excluding FCS, is two bytes. A single byte
payload is illegal. The HDLC controller delivers data to the Transmit Channel
Assigner block (TCAS672) on demand. A packet in progress is aborted if an
under-run occurs. The THDL672 is programmable to operate in transparent
mode where packet data retrieved from the PCI host is transmitted verbatim.
9.8.1 Transmit HDLC Processor
The HDLC processor is a time-slice state machine which can process up to 672
independent channels. The state vector and provisioning information for each
channel is stored in a RAM. Whenever the TCAS672 requests data, the
appropriate state vector is read from the RAM, processed and finally written back
to the RAM. The HDLC state-machine can be configured to perform flag
insertion, bit stuffing and CRC generation. The HDLC processor requests data
from the partial packet processor whenever a request for channel data arrives.
However, the HDLC processor does not start transmitting a packet until the entire
packet is stored in the channel FIFO or until the FIFO free space is less than the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
77
PMC [ PMC-SIERRA, INC ]
