RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
software programmable limit. If a channel FIFO under-runs, the HDLC processor
aborts the packet.
The configuration of the HDLC processor is accessed using indirect channel
read and write operations. When an indirect operation is performed, the
information is accessed from RAM during a null clock cycle inserted by the
TCAS672 block. Writing new provisioning data to a channel resets the channel’s
entire state vector.
9.8.2 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO. Figure 16 shows an example of three blocks (blocks 1, 3, and
200) linked together to form a 48 byte channel FIFO. The three pointer values
would be written sequentially using indirect block write accesses. When a
channel is provisioned with this FIFO, the state machine can be initialised to
point to any one of the three blocks.
The partial packet buffer processor is divided into three sections: reader, writer
and roamer. The roamer is a time-sliced state machine which tracks each
channel's FIFO buffer free space and signals the writer to service a particular
channel. The writer requests data from the TMAC672 block and transfers packet
data from the TMAC672 to the associated channel FIFO. The reader is a time-
sliced state machine which transfers the HDLC information from a channel FIFO
to the HDLC processor when the HDLC processor requests it. If a buffer under-
run occurs for a channel, the reader informs the HDLC processor and purges the
rest of the packet.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
78
PMC [ PMC-SIERRA, INC ]
