RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
the free space is greater than the limit set by XFER[3:0]. The roamer also
decrements the end-of-packet count when the reader signals that it has passed
an end of a packet to the HDLC processor. If the HDLC is transmitting a packet
and the FIFO free space is greater than the starving trigger level and there are
no complete packets within the FIFO (end-of-packet count equal to zero), a per-
channel starving flag is set. The roamer searches the starving flags in a round-
robin fashion to decide which channel FIFO should make expedited data
requests to the TMAC672 block. If no starving flags are set, the roamer
searches the request flags in a round-robin fashion to decide which channel
FIFO should make regular data requests to the TMAC672 block. The roamer
informs the partial packet writer of the channel FIFO to process, the FIFO free
space and the type of request it should make. The writer sends a request for
data to the TMAC672 block, writes the response data to the channel FIFO, and
sets the block full flags. The writer reports back to the roamer the number of
blocks and end-of-packets transferred. The maximum amount of data
transferred during one request is limited by a software programmable limit
(XFER[3:0]).
The configuration of the HDLC processor is accessed using indirect channel
read and write operations as well as indirect block read and write operations.
When an indirect operation is performed, the information is accessed from RAM
during a null clock cycle identified by the TCAS672 block. Writing new
provisioning data to a channel resets the entire state vector.
9.9 Transmit Channel Assigner
The Transmit Channel Assigner block (TCAS672) processes up to 672 channels.
Data for all channels is sourced from a single byte-serial stream from the
Transmit HDLC Controller / Partial Packet Buffer block (THDL672). The
TCAS672 demultiplexes the data and assigns each byte to any one of 32 links.
Each link may be configured to support 2.048 or 8.192 H-MVIP traffic, to support
T1/J1/E1 channelised traffic or to support unchannelised traffic. When
configured to support H-MVIP traffic, each group of 8 links share a clock and
frame pulse, otherwise each link is independent and has its own associated
clock. For each high-speed link (TD[2:0]), the TCAS provides a six byte FIFO.
For the remaining links (TD[31:3]), the TCAS provides a single byte holding
register. The TCAS672 also performs parallel to serial conversion to form a bit-
serial stream. In the event where multiple links are in need of data, TCAS672
requests data from upstream blocks on a fixed priority basis with link TD[0]
having the highest priority and link TD[31] the lowest.
From the point of view of the TCAS672, links configured for H-MVIP traffic
behave identically to links configured for T1/J1/E1 channelised or unchannelised
traffic in the back end, only differing on the link side as described herein. First,
the number of time-slots in each frame is programmable to be 32 or 128 and has
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
80
PMC [ PMC-SIERRA, INC ]
