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PM7380-PI 参数 Datasheet PDF下载

PM7380-PI图片预览
型号: PM7380-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
packet P3. The TMAC672 indicates valid horizontal links by setting the V bit to  
logic 1.  
9.7.2 Task Priorities  
The TMAC672 must perform a number of tasks concurrently in order to maintain  
a steady flow of data through the system. The main tasks of the TMAC672 are  
managing the Ready Queue (i.e. removing chains of data packets from the  
queue and attaching them to the appropriate per-channel linked list) and  
servicing requests for data from the Transmit Packet Interface. The priority of  
service for each of the tasks is fixed by the TMAC672 as follows:  
Sꢀ Top priority is given to servicing ‘expedited’ read requests from the Transmit  
HDLC Processor / Partial Packet Buffer block (THDL672).  
Sꢀ Second priority is given to removing chains of data packets from the TDRR  
queue and attaching them to the appropriate per-channel linked list.  
Sꢀ Third priority is given to servicing non-expedited read requests from the  
THDL672.  
9.7.3 DMA Transaction Controller  
The DMA Transaction Controller coordinates the processing of requests from the  
THDL672 with the reading of data stored in host memory. The reading of a data  
packet may require a number of separate host memory transactions, interleaved  
with transactions of other DMA channels. As well as reading data from the Host  
Master Interface, the DMA Transaction Controller initiates read and write  
transactions to the PCI Controller block (GPIC) for the purposes of maintaining  
the data structures (queues, descriptors, etc.) in host memory.  
9.7.4 Read Data Pipeline  
The Read Data Pipeline inserts delay in the data stream between the GPIC  
interface and the THDL672 interface to enable the DMA Transaction Controller to  
generate appropriate control signals at the Transmit Packet Interface.  
9.7.5 Descriptor Information Cache  
The Descriptor Information Cache provides the storage for the Transmit Channel  
Descriptor Reference (TCDR) Table.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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