RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Table 29 – Test Mode Register Memory Map
Address TA[12:0] Register
0x0000 - 0x07FC Normal Mode Registers
0x0800 - 0x107C
0x1080 - 0x10FC
0x1100 - 0x11FC
0x1200 - 0x123C
0x1240 - 0x127C
0x1280 - 0x12FC
0x1300 - 0x137C
0x1380 - 0x13BC
0x13C0 - 0x13FC
0x1400 - 0x14FC
0x1500 - 0x151C
0x1520 - 0x1FFC
Reserved
GPIC Test Registers
RCAS Test Registers
RHDL Test Registers
Reserved
RMAC Test Registers
TMAC Test Registers
THDL Test Registers
Reserved
TCAS Test Registers
PMON Test Registers
Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence unused register bits
should be masked off by software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise
noted.
12.2 JTAG Test Port
The FREEDM-32P672 JTAG Test Access Port (TAP) allows access to the TAP
controller and the 4 TAP registers: instruction, bypass, device identification and
boundary scan. Using the TAP, device input logic levels can be read, device
outputs can be forced, the device can be identified and the device scan path can
be bypassed. For more details on the JTAG port, please refer to the Operations
section.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
264
PMC [ PMC-SIERRA, INC ]
