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PM7380-PI 参数 Datasheet PDF下载

PM7380-PI图片预览
型号: PM7380-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
12  
TEST FEATURES DESCRIPTION  
The FREEDM-32P672 also supports a standard IEEE 1149.1 five signal JTAG  
boundary scan test port for use in board testing. All device inputs may be read  
and all device outputs may be forced via the JTAG test port.  
12.1 Test Mode Registers  
Test mode registers are used to apply test vectors during production testing of  
the FREEDM-32P672. Production testing is enabled by asserting the PMCTEST  
pin. During production tests, FREEDM-32P672 registers are selected by the  
TA[12:0] pins. The address of a register on TA[12:0] is identical to the PCI offset  
of that register when production testing is disabled (PMCTEST low). Read  
accesses are enabled by asserting TRDB low while write accesses are enabled  
by asserting TWRB low. Test mode register data is conveyed on the TDAT[15:0]  
pins. Test mode registers (as opposed to normal mode registers) are selected  
when TA[12]/TRS is set high.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
263  
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