RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Pin Name
Type
Pin No.
Function
-PI
-BI
TRSTB
Input
J3
J17
The active low test reset signal (TRSTB) provides an
asynchronous FREEDM-8 test access port reset via
the IEEE P1149.1 test access port. TRSTB is an
asynchronous input with an integral pull up resistor.
Note that when TRSTB is not being used, it must be
connected to the RSTB input.
VBIAS[3:1]
Input
J2
U4
D4
The bias signals (VBIAS[3:1]) provide 5 Volt bias to
input and I/O pads to allow the FREEDM-8 to tolerate
connections to 5 Volt devices. To avoid damage to the
device, the VBIAS[3:1] signals must be connected
together externally and must at all times be kept at a
voltage that is equal to or higher than the VDD[28:1]
power supplies. In a 3.3V operating environment,
VBIAS[3:1] and VDD[28:1] may be connected
together. In a 5V operating environment, VBIAS[3:1]
should be powered up to 5V before VDD[28:1] are
powered up to 3.3V.
B19
W19 H20
EN5V
Input
C4
D17
The 5 Volt PCI signalling enable signal (EN5V)
causes the PCI Host Interface Signals to operate in
the 5V PCI signalling environment when set high and
the 3.3V PCI signalling environment when set low.
EN5V is an asynchronous input with an integral pull
up resistor.
Table 4 – Production Test Interface Signals (30)
Pin Name
Type
Pin No.
-BI
Function
-PI
TA[0]
TA[1]
TA[2]
TA[3]
TA[4]
TA[5]
TA[6]
TA[7]
TA[8]
TA[9]
TA[10]
Input
D7
B6
A6
A7
B8
D9
B9
D10
B10
A11
B11
B16
C15
A15
D13
A14
D12
C12
A12
C11
A11
B10
The test mode address bus (TA[10:0]) selects specific
registers during production test (PMCTEST set high)
read and write accesses.
In normal operation (PMCTEST set low), TA[10:0]
should be tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
25
PMC [ PMC-SIERRA, INC ]
