RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Table 3 – Miscellaneous Interface Signals (12)
Pin Name
Type
Pin No.
-BI
Function
-PI
SYSCLK
Input
J4
H19
The system clock (SYSCLK) provides timing for the
core logic. SYSCLK is nominally a 50% duty cycle 25
MHz to 33 MHz clock.
RSTB
Input
Input
U14
V15
W5
The active low reset signal (RSTB) signal provides an
asynchronous FREEDM-8 reset. RSTB is an
asynchronous input. When RSTB is set low, all
FREEDM-8 registers are forced to their default
states. In addition, TD[7:0] are forced high and all
PCI output pins are forced tri-state and will remain
high or tri-stated, respectively, until RSTB is set high.
PMCTEST
U6
The PMC production test enable signal (PMCTEST)
places the FREEDM-8 is test mode. When
PMCTEST is set high, production test vectors can be
executed to verify manufacturing via the test mode
interface signals TA[10:0], TA[11]/TRS, TRDB, TWRB
and TDAT[15:0]. PMCTEST must be tied low in
normal operation.
TCK
TMS
Input
Input
Input
K2
J1
J19
J18
The test clock signal (TCK) provides timing for test
operations that can be carried out using the IEEE
P1149.1 test access port. TMS and TDI are sampled
on the rising edge of TCK. TDO is updated on the
falling edge of TCK.
The test mode select signal (TMS) controls the test
operations that can be carried out using the IEEE
P1149.1 test access port. TMS is sampled on the
rising edge of TCK. TMS has an integral pull up
resistor.
TDI
K3
K1
K19
K18
The test data input signal (TDI) carries test data into
the FREEDM-8 via the IEEE P1149.1 test access
port. TDI is sampled on the rising edge of TCK.
TDI has an integral pull up resistor.
TDO
Tristate
Output
The test data output signal (TDO) carries test data
out of the FREEDM-8 via the IEEE P1149.1 test
access port. TDO is updated on the falling edge of
TCK. TDO is a tri-state output which is inactive
except when scanning of data is in progress.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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