RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Ball
Ball
Type No. Function
Name
CAVD
CAVS
RAVD
RAVS
TAVD
Analog M3 The power (CAVD) pins for the analog clock synthesis
Power N3 unit. These pins should be connected to analog
+3.3V.
Analog L3 The ground (CAVS) pins for the analog clock
Ground M2 synthesis unit. These pins should be connected to
analog GND.
Analog H2 The power (RAVD) pins for the LVDS receivers.
Power L4 These pins should be connected to analog +3.3V.
T2
Analog J3
The ground (RAVS) pins for the LVDS receivers.
Ground N4 These pins should be connected to analog GND.
R3
Analog D5 The power (TAVD) pins for the LVDS transmitters.
Power G2 These pins should be connected to analog +3.3V.
H3
J2
R1
U1
U2
Y5
TAVS
Analog C4 The ground (TAVS) pins for the LVDS transmitters.
Ground E3 These pins should be connected to analog GND.
G1
J1
R2
T3
W3
AA4
Notes on Pin Description:
1.
All S/UNI-VORTEX inputs and bi-directionals present minimum capacitive
loading and operate at TTL logic levels, except RXD0+/- through RXD7+/-.
2.
Inputs RSTB, ALE, RANYPHY, TMS, TDI, TCK and TRSTB have internal
pull-up resistors. To improve noise immunity, in designs where these
inputs are no-connects it is still recommend that they be tied to VDD.
3.
The recommended power supply sequencing is as follows:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
27
PMC [ PMC-SIERRA, INC ]
