RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Fig. 12 Downstream Any-PHY Interface Polling Timing
TCLK
TADR[11:0]
TPA
X
A
X
B
X
C
D
X
X
Fig. 13 is an example of the functional timing of the transfer aspect of the
downstream cell interface. In this example, the user prepend is included in the
data structure. A transfer is permitted when polling has established a buffer is
available for the elected logical channel. The TSX input initiates the cell transfer
as well as identifying the inband address (W0). The cell is accepted if the inband
address is within the ranges defined by the Control Channel Base Address,
Logical Channel Base Address and Logical Channel Address Range registers;
otherwise, it is ignored.
It is permissible for TENB to be held low because a cell transfer is only initiated
upon TSX assertion and automatically terminates upon the last word (W28) of
the cells. TENB is ignored when TSX is high. The existence of TENB allows the
master to pause a cell transfer as shown in Fig. 13.
Fig. 13 Downstream Any-PHY Interface Transfer Timing
TCLK
TENB
TSX
TDAT[15:0]
TPRTY
W 27 W 28
X
X
X
X
W 0
W 1
W 2
W 3
X
X
W 4
W 5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
146
PMC [ PMC-SIERRA, INC ]
