RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
The interface responds to the polling of address “A” (which equals VADR[4:0]) by
asserting RPA. As a result, the master selects the S/UNI-VORTEX by presenting
“A” again during the last cycle RENB is high. Had not the device been selected,
RSX, RSOP, RDAT[15:0] and RPRTY would have remained high-impedance.
Fig. 11 illustrates that a cell transfer may be paused by deasserting RENB. No
explicit reselection is required to resume the transfer, only reassertion of RENB.
Upon completion of the cell transfer, the interface autonomously deselects itself.
As a result, it is permissible to hold RENB low beyond the end of the cell transfer
as shown.
Fig. 11 Upstream Any-PHY Interface Timing
Fig. 12 is an example of the functional timing of the polling aspect of the
downstream cell interface. Addresses “A”, “C” and “D” lie within the address
space defined by the Control Channel Base Address, Logical Channel Base
Address and Logical Channel Address Range registers; therefore, the device
responds to those polls. The polls of logical channels “C” and “D” illustrate that
polls in consecutive cycles are permitted.
Once a logic high is returned on TPA in response to a poll, a cell may be
transferred as per Fig. 13.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
145
PMC [ PMC-SIERRA, INC ]
