RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
13
FUNCTIONAL TIMING
While the following diagrams present representative waveforms, they are not an
attempt to unambiguously describe the interfaces. The Pin Description section is
intended to present the detailed pin behavior and constraints on use.
Fig. 10 gives an example of the functional timing of the upstream interface when
configured as a 16-bit SCI-PHY Level 2 compliant slave. The interface is
programmed to include a user prepend (W1) as well the inband address (W0).
The interface responds to the polling of address “A” (which equals VADR[4:0]) by
asserting RPA. As a result, the master selects the S/UNI-VORTEX by presenting
“A” again during the last cycle RENB is high. Had not the device been selected,
RSX, RSOP, RDAT[15:0] and RPRTY would have remained high-impedance.
Fig. 10 illustrates that a cell transfer may be paused by deasserting RENB. The
device is reselected by presenting address “A” the last cycle RENB is high to
resume the transfer.
Fig. 10 Upstream SCI-PHY Interface Timing
Fig. 11 gives an example of the functional timing of the upstream interface when
configured as a 16-bit Any-PHY compliant slave. The user prepend (W1) is
excluded in this example. Note that relative to SCI-PHY mode, all outputs have
an additional cycle latency.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
144
PMC [ PMC-SIERRA, INC ]
