RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
9.7.3 Reading Cells
The microprocessor cell buffer has a capacity of four cells. The UPCA bit
returned on the upstream high-speed serial link will be set to logic 0 when the
buffer contains more than two cells. This shall prevent overflow of the local
buffer if the indication is responded to within two cell slots.
Maskable interrupt status bits are generated upon the receipt of the first cell,
upon detection of a CRC-32 error and upon a buffer overflow. If a buffer
overflow occurs (this would indicate an operation failure due to the far-end
device not respecting the UPCA bit status), entire cells are lost (the new
incoming cells would be lost).
The format of received cell when it is read from the Microprocessor Cell Buffer
Data register is shown in Fig. 11. Unused bytes have undefined value. The
value of the bytes marked with an asterisk depends on the configuration of the
corresponding LVDS link and the source of the cell. This is discussed further in
the Operations section.
See Section 12.1.2 for details on the cell read protocol.
9.8 Internal Registers
The microprocessor interface provides access to normal and test mode registers.
The normal mode registers are required for mission mode operation, and test
mode registers are used to enhance the testability of the S/UNI-DUPLEX. The
register set is accessed as follows:
9.9 Register Memory Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
Register
Master Reset and Identity / Load Performance Meters
Master Configuration
Master Interrupt Status
Miscellaneous Interrupt Statuses
Clock Monitor
Serial Links Maintenance
Extended Address Match (LSB)
Extended Address Match (MSB)
Extended Address Mask (LSB)
Extended Address Mask (MSB)
Output Address Match
Configuration Pins Status
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
80
PMC [ PMC-SIERRA, INC ]
