RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
The microprocessor cell format is illustrated in Fig. 11. The 8-bit cell data
structure is fixed at 60 bytes long regardless of how the SCI-PHY/Utopia/Any-
PHY bus (or the Clocked Serial Data interface) and LVDS link are configured.
The microprocessor must transfer all bytes of the cell, including the unused
ones. The unused bytes are included in the received cell when it is made
available to the far-end microprocessor, but the value of the bytes is undefined.
This 60 bytes cell format is used to retain interface compatibility with the PM7326
S/UNI-APEX device, and to align the header and data fields on 32 bit
boundaries.
Bytes marked with an asterisk in Fig. 11 must be included in cells written into the
cell transfer register, but they will only be sent across the LVDS if the
corresponding Transmit High-Speed Serial Configuration register (0x60) and the
far-end’s corresponding Receive High-Speed Serial Configuration register have
been programmed to include them. See Section 12.2 for details.
Other than what has already been mentioned, there are no constraints on the
contents of cells written by the microprocessor. They are transported across the
LVDS link transparently. Specifically, although the standard ATM header bytes
H1-H5 are shown in Fig. 11 there is no restriction on the values they can contain.
See Section 12.1.1 for details on the cell write protocol.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
78
PMC [ PMC-SIERRA, INC ]
