RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
The rising edge of TX8K initializes an internal counter to the number of bytes in
the high-speed serial cell minus one. The counter decrements with each byte
transmitted. Upon the fourth byte of the next extended cell, the state of the
counter is encoded in the TREF[5:0] field. If no rising edge on TX8K has
occurred, TREF[5:0] is set to all ones.
In the receive direction, two independent counters are initialized to the value of
TREF[5:0] extracted from RXD1+/- or RXD2+/-. The counters decrement with
each byte received on its respective high-speed serial link. When the count
becomes zero, a rising edge is generated on an internal reference signal
associated to this counter. If the value of TREF[5:0] is all ones, the signal
remains low. The internal reference signal of the high-speed serial link that is
declared active is output on RX8K.
If the same functionality is implemented at the far end of the serial link, it can be
seen that the recovered timing event is generated one cell period later than the
inserted timing with a resolution of one byte. Because of the limited edge
encoding resolution, some jitter is present. At a link rate of 155.52 Mb/s, 63ns of
peak-to-peak jitter will occur on RX8K. A local high-Q phase locked loop (PLL)
can be used to remove the jitter.
In systems where 1:1 protection is used the timing reference output on TX8K will
change sources if the link marked active changes. Even though the S/UNI-
DUPLEX maintains the edges being sent on both links, and even if the far end
sources are synchronized, there is no guarantee that an arbitrary phase hit will
not occur during protection switching.
In general the LVDS links will run error free, but if errors do occur the S/UNI-
DUPLEX discards a cell that arrive with an HCS error. Hence it is possible that a
transmission error could corrupt the cell carrying a clock edge indication in
TREF[5:0]. This would result in that edge being lost (i.e. there would be no
corresponding output on TX8K).
9.6 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan.
The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The S/UNI-DUPLEX identification code is 173500CD
hexadecimal.
9.7 Microprocessor Interface
The microprocessor interface is provided for device configuration and status
monitoring by an external microprocessor. Normal mode registers and test mode
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
76
PMC [ PMC-SIERRA, INC ]
