RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
The receivers monitor for loss of signal (LOS) on the links. LOS is declared
upon 2048 bit periods (13.2 µs at 155.52 Mb/s) without a signal transition in the
scrambled data. As a consequence, a status bit is set, a maskable interrupt is
asserted and the RDI (Remote Defect Indication) codeword is sent repetitively in
the BOC bit in the corresponding downstream link. The LOS indication is
cleared when a signal transition has occurred in each of 16 consecutive intervals
of 16 bit periods each.
Clock recovery is performed by a digital phase locked loop (DPLL). The
implementation is robust against operating condition variations and power supply
noise. The receive link is constrained to be within 100 ppm of eight times the
REFCLK frequency.
As shown in Fig. 10, two datapath loopbacks are provided on each LVDS link to
aid in fault isolation and continuity verification. The metallic loopback routes
high-speed serial receive data to the transmitter. The diagnostic loopback
replaces the downstream data with the upstream data. The loopbacks can be
enabled individually or simultaneously, and each link can be looped back
independently of the other.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
65
PMC [ PMC-SIERRA, INC ]
