RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
after clock recovery. Setting the DLB bit corresponding to the inactive link has no
effect.
The metallic loopback is set independently on each high-speed serial link. It can
be effected in one of three ways: after the receipt of the loopback activate code
on the corresponding RXD1+/- or RXD2+/- inputs (as described in Section 9.3.2)
when the corresponding MLB1 or MLB2 bit of the Serial Link Maintenance
register is set to logic 1 or when the reset (RSTB) input is asserted low. The
loopback occurs at the LVDS transceiver after the conversion to digital but before
clock recovery. The looped back data may be slightly distorted by the data
slicing (differential to single-ended) and re-buffering that occurs.
Metallic loopback is terminated if a loopback deactivate bit oriented code is
received and validated, provided the corresponding MLB1 or MLB2 bit of the
Serial Links Maintenance register to logic 0.
9.3.1 Link Integrity Monitoring
Although the serial link bit error rate can be inferred from the accumulated
Header Check Sequence (HCS) errors, the option exists to perform error
monitoring over the entire bit stream.
When the feature is enabled the second User Prepend byte transmitted shall be
overwritten by the CRC-8 syndrome for the preceding cell. The encoding is valid
for all cells, including stuff cells. The CRC-8 polynomial is x8 + x2 + x + 1. The
receiver shall raise a maskable interrupt and optionally increment the HCS error
count. Simultaneous HCS and cell CRC-8 errors result in a single increment.
9.3.2 Bit Oriented Codes
Bit Oriented Codes (BOCs) are carried in the BOC bit position in the System
Prepend. The 63 possible codes can be used to carry predefined or user
defined signaling.
Bit oriented codes are transmitted as a repeating 16-bit sequence consisting of 8
ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). The code to be
transmitted is set independently on the two LVDS links, and is programmed by
writing the TXD1 Bit Oriented Code and TXD2 Bit Oriented Code registers. The
autonomously generated Remote Defect Indication (RDI) code, which is
generated upon a loss-of-signal or loss-of-cell-delineation, takes precedence
over the programmed code. RDI insertion can be disabled via the RDIDIS bit of
the Serial Links Maintenance register. RDI can be inserted manually on a high-
speed serial link by setting the corresponding TXD1 Bit Oriented Code or TXD2
Bit Oriented Code register to all zeros.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
67
PMC [ PMC-SIERRA, INC ]
