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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
9.3 High-Speed Serial Interface  
The S/UNI-DUPLEX provides backplane interconnection via 100 to 200 Mb/s  
serial links. All data destined to and coming from the core cell processing card  
are concentrated on these high-speed links. The transceivers support UTP-5  
cable lengths up to 10m. To avoid clock skew issues, no clock is transmitted and  
the receivers recover a local clock from the incoming data.  
Two bi-directional LVDS links are provided for redundancy; each link is intended  
to be routed to different core cards. Both LVDS transmitters carry identical traffic  
except for internally generated overhead. Both links are frequency locked to the  
single input reference clock although their phase is not guaranteed to match. At  
the LVDS receivers clock recovery and cell delineation are always active for both  
receivers to allow a quick switch to the redundant core card with minimal cell  
loss.  
The serial links carry ATM cells with prepended bytes. The cell format is  
illustrated in Fig. 9 and discussed in Section 12.2). The S/UNI-DUPLEX  
appends the first four bytes and the Header Check Sequence (HCS) byte in the  
upstream direction and strips them off and parses them in the downstream  
direction. The remainder of the bytes in the data structure are transferred  
transparently. The bytes are serialized most significant bit first. The bit stream is  
a simple concatenation of the extended cells. Cell rate decoupling is  
accomplished through introduction of stuff cells.  
The transmitter inserts a correct CRC-8 that protects both the ATM cell header  
and prepended bytes in the HCS byte. Cells with an errored HCS are counted  
and then discarded. The receiver also uses the HCS byte for determining cell  
delineation. Failure to establish cell alignment results in a loss of cell delineation  
(LCD) alarm. The entire bit stream is scrambled with a x43 + 1 self-synchronous  
scrambler.Table 16 summarizes the contents of the system prepended bytes.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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