RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 9 High-Speed Serial Link Data Structure
Byte 0 1 2 3
4+N
User Header
4 to 6 bytes
H
C
S
ATM Payload
48 bytes
ATM Payload
System
Prepend
User
Prepend
N bytes,
where N = 0 or 2 Table 16 Prepended Fields
Byte
Bits
Mnemonic
Description
0
7:0
CA[15:8]
The CA[15:0] bits carry per-PHY flow
control information in the upstream
direction. To support 32 PHYs, the status
for each PHY is sent every other cell; the
CASEL indicates which half is represented.
If CASEL is logic 0, CA[15:0] corresponds
to those PHYs with addresses 0 through
15. If CASEL is logic 1, CA[15:0]
1
7:0
CA[7:0]
corresponds to those PHYs with
addresses 16 through 31.
In the downstream direction, CA[15:0]
communicates congestion of the upstream
entity. The encoding is identical to the
upstream direction. A logic 0 indicates the
far end can accept no more cells for a
specific logical channel. A logic 1 indicates
the S/UNI-DUPLEX is free to send queued
traffic for that logical channel immediately.
In the event of an errored header (as
detected by an incorrect HCS), the CA bits
will be assumed to be all zero. This
ensures cells are not transmitted for which
there is no buffer space.
2
7
CASEL
The state of the CA select bit determines
which half of the PHY devices the CA[15:0]
bits correspond to. CASEL toggles with
each cell transmitted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
62
PMC [ PMC-SIERRA, INC ]
