RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Table 12 Sixteen Bit Any-PHY Bus Slave, Input Configuration
Word
1
Register 0x0C
H5UDF PRELEN
Notes
#
bytes
54
0
4
Y
Y
Y
Y
N
N
Y
Y
N
Y
N
Y
0
1
0
1
00
00
01
01
PHY ID word, then H1-H4, no H5/UDF field
Default, PHY ID, H1-H4, then H5/UDF
PHY ID, user word, then H1-H4, no H5/UDF
PHY ID, user word, H1-H4, then H5/UDF
56
56
58
In the egress direction (cells are transferred from the LVDS to the output port),
the port appears as a single addressable Any-PHY slave. The S/UNI-DUPLEX
autonomously multiplexes the traffic from up to 32 logical channels and presents
it as a single cell stream on the output bus. If at least one cell is present in any
of the FIFOs, OCA will drive high when the device is polled. OCA is delayed by
an additional clock cycle (one OFCLK) in the Any-PHY configuration.
Polling occurs when OAVALID is sampled low and the sampled OADDR[4:0]
matches the OAD[4:0] bits in the Output Address Match register.
A cell transfer will be enacted if the OADDR[4:0] value equals the state of the
OAD[4:0] bits in the Output Address Match register when the OENB is last
sampled high. A word prepended to the transferred ATM cell identifies the logical
channel. The three most significant bits of the prepend in the 8-bit format and
the 11 most significant bits of the prepend in the 16-bit format are derived from
the contents of the Extended Address Match registers, which default to all zeros.
Table 13 summarizes the distinctions between the two protocols in the egress
direction.
Table 13 SCI-PHY/Utopia and Any-PHY Comparison, Egress Direction
Attribute
Latency
SCI-PHY/Utopia
Any-PHY
ODAT[15:0], OPRTY and OSOC are
driven or become high impedance
immediately upon sampling OENB
low or high, respectively. OCA is
driven immediately upon sampling a
OADDR[4:0] value that matches the
contents of the Output Address
Match register.
0DAT[15:0], 0PRTY, 0SOC and OSX
are driven or become high impedance
on the OFCLK rising edge following the
one that samples OENB low or high,
respectively. OCA is driven on the
OFCLK rising edge following the one
that samples a OADDR[4:0] value that
matches the content of the Output
Address Match register.
OSX
Undefined. It is low when not high
impedance.
High coincident with the first word of
the cell data structure.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
54
PMC [ PMC-SIERRA, INC ]
