欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7350-PI的Datasheet PDF文件第60页浏览型号PM7350-PI的Datasheet PDF文件第61页浏览型号PM7350-PI的Datasheet PDF文件第62页浏览型号PM7350-PI的Datasheet PDF文件第63页浏览型号PM7350-PI的Datasheet PDF文件第65页浏览型号PM7350-PI的Datasheet PDF文件第66页浏览型号PM7350-PI的Datasheet PDF文件第67页浏览型号PM7350-PI的Datasheet PDF文件第68页  
RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
Table 9 Sixteen Bit SCI-PHY/Utopia Bus Slave, Output Configuration  
Word  
Register 0x14  
INADD  
H5  
PRE  
Notes  
H1-H4 only, no PHY ID  
Default, Utopia compatible, no PHY ID  
2 user bytes, H1-H4, no PHY ID  
2 user bytes, H1-H4, H5/UDF, no PHY ID  
Most common setting when Utopia  
compatibility is desired. Standard 54  
byte cell, PHY ID embedded in H5/UDF.  
2 user bytes, H1-H4, PHY ID in H5/UDF  
#
bytes  
52  
0
1
4
UDF  
0
UDF  
LEN  
00  
00  
01  
01  
00  
N
N
N
N
N
N
N
Y
Y
N
N
Y
N
Y
Y
0
1
0
1
X
54  
0
54  
0
56  
0
54  
1
56  
N
Y
Y
1
X
01  
9.1.3 Any-PHY Slave  
The Any-PHY bus slave format is enabled when the IANYPHY and OANYPHY  
inputs are high, and IMASTER, and OMASTER inputs are all tied low.  
In the ingress direction (cells are transferred from the parallel bus input port to  
the LVDS links), the port presents itself as 32 PHY entities. Cells read from the  
bus are queued in a dedicated FIFO for each logical channel. As in the SCI-PHY  
bus mode, the ability of the FIFOs to accept additional cells is discovered  
through polling using the IADDR[4:0] and IAVALID inputs. Upon IAVALID being  
sampled low (note this is opposite to SCI-PHY mode) the ICA output is asserted  
if the cell FIFO for the logical channel addressed by IADDR[4:0] has at least one  
empty cell buffer. If the FIFO is full, ICA is deasserted. If a cell transfer is in  
progress that will fill a logical channel FIFO, ICA will also be deasserted. If  
IAVALID is sampled high ICA becomes high impedance. ICA is delayed by one  
bus cycle (i.e. one IFCLK cycle) in the Any-PHY bus configuration.  
In Any-PHY mode cell transfer is initiated using inband selection. The first word  
of the cell, coincident with the assertion of the ISX signal, is used for logical  
channel selection. Cells are accepted by the S/UNI-DUPLEX if the value in the  
Extended Address field of Word 0 agrees with the Extended Address Match  
registers over the range of bits specified by the Extended Address Mask  
registers.  
Table 10 summarizes the distinctions between the SCI-PHY/Utopia and Any-PHY  
protocols in the ingress direction.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
52  
 复制成功!