RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
identifier and an inband address can be included in an additional prepend word
or in the H5/UDF fields, as discussed below. By default, none of the optional
words are prepended, and the H5 or H5/UDF field is included.
Be aware that cells are transported transparently across the LVDS links. There
are no constraints on the contents. Therefore, data streams other than ATM
cells can be transferred across the parallel bus interface interface; only the bus
timing and bus protocols need be respected.
It is also important to note that the treatment of the H5/UDF field, the address
prepend (Word 0), and the optional User Prepend on the input and output buses
are independent from how their corresponding fields on the LVDS link are
configured. See Section 12.2 for further details.
9.1.1 SCI-PHY or Utopia Bus Master
The SCI-PHY/Utopia bus master format is enabled when the IANYPHY and
OANYPHY inputs are tied low and the IMASTER and OMASTER inputs are tied
high. The SCI-PHY/Utopia bus master interface supports up to 32 PHY entities
provided the IAVALID and OAVALID signals are used; otherwise, 31 are
supported. The interface is fully Utopia Level 2 compliant when IAVALID and
OAVALID are not used. It is assumed the PHY devices perform all Transmission
Convergence (TC) functions including cell delineation, cell rate decoupling,
payload scrambling, HCS insertion and cell filtering upon header errors.
In the ingress direction (cells are transferred from the input bus to the LVDS link),
the S/UNI-DUPLEX uses round robin polling to provide equal access to all PHY
devices. As directed by flow control information on the LVDS link (and optionally
through S/UNI-DUPLEX configuration), any PHY device may temporarily be
removed from the polling sequence. Data transfers are cell based, that is, an
entire cell is transferred from one PHY device before another is selected. Polling
occurs concurrently with cell transfers to ensure maximum throughput.
The SCI-PHY/Any-PHY Input Configuration 1 register (0x0C) determines the cell
format of the input bus. Unlike the Any-PHY bus mode, a SCI-PHY/Utopia bus
master does not require and hence does not support embedded PHY ID. The
cell length options for the 8 bit bus (shown in Fig. 6) are described in Table 2. 16
bit bus options (shown in Fig. 7) are described in Table 3.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
47
PMC [ PMC-SIERRA, INC ]
