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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
bus formats need not be the same. When configured as a SCI-PHY or Utopia  
Level 2 interface the S/UNI-DUPLEX can be either a bus master or bus slave, as  
determined by the IMASTER and OMASTER inputs. When configured as an  
Any-PHY interface, the S/UNI-DUPLEX can only be a bus slave. 8 and 16 bit  
wide interfaces are supported in all configurations, and are determined by the  
IBUS8 and OBUS8 inputs.  
Table 1 Signal Name Cross-Reference  
S/UNI-  
DUPLEX  
PIN Name  
UTOPIA  
Level 2  
Bus Slave  
UTOPIA  
Level 2  
Bus Master  
SCI-PHY  
Level 2  
Bus Slave  
SCI-PHY Any-PHY Bus  
Level 2  
Slave  
Bus Master  
IFCLK  
TxClk  
RxClk  
RxEnb*  
RxAddr[4:0]  
n/a  
TFCLK  
RFCLK  
RWRENB  
RADDR[4:0]  
RAVALID  
RDAT[15:0]  
RPRTY  
RCA  
TCLK  
IENB  
TxEnb*  
TxAddr[4:0]  
n/a  
TWRENB  
TADDR[4:0]  
TAVALID  
TDAT[15:0]  
TPRTY  
TCA  
TENB  
IADDR[4:0]  
IAVALID  
IDAT[15:0]  
IPRTY  
TADR[4:0]  
TADR[5]  
TDAT[15:0]  
TPRTY  
TPA  
TxData[15:0]  
TxPrty  
RxData[15:0]  
RxPrty  
RxClav  
RxSOC  
n/a  
ICA  
TxClav  
TxSOC  
n/a  
ISOC  
TSOC  
RSOC  
TSOP  
ISX  
n/a  
n/a  
TSX  
OFCLK  
OENB  
RxClk  
TxClk  
RFCLK  
RWRENB  
RADDR[4:0]  
RAVALID  
RDAT[15:0]  
RPRTY  
RCA  
TFCLK  
RCLK  
RxEnb*  
RxAddr[4:0]  
n/a  
TxEnb*  
TxAddr[4:0]  
n/a  
TWRENB  
TADDR[4:0]  
TAVALID  
TDAT[15:0]  
TPRTY  
TCA  
RENB  
OADDR[4:0]  
OAVALID  
ODAT[15:0]  
OPRTY  
OCA  
RADR[4:0]  
RADR[5]  
RDAT[15:0]  
RPRTY  
RPA  
RxData[15:0]  
RxPrty  
RxClav  
RxSOC  
n/a  
TxData[15:0]  
TxPrty  
TxClav  
TxSOC  
n/a  
OSOC  
RSOC  
TSOC  
RSOP  
OSX  
n/a  
n/a  
RSX  
Utopia and SCI-PHY are electrically compatible, the only difference is that Utopia  
does not support the use of the optional OAVALID and IAVALID pins. Therefore,  
whether the input and output buses are Utopia or SCI-PHY is determined by the  
inclusion or exclusion of optional words in the cell format that is transferred  
across the bus. The cell formats supported are presented in Fig. 6 and Fig. 7. As  
programmed through register bits, bytes may be prepended to a basic ATM cell  
to support applications where user defined context information is carried inband.  
Also, inclusion of the H5 and H5/UDF fields (8 bit and 16 bit modes respectively)  
is optional under most configurations. For bus slave configurations, the PHY  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
46  
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