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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7350-PI的Datasheet PDF文件第49页浏览型号PM7350-PI的Datasheet PDF文件第50页浏览型号PM7350-PI的Datasheet PDF文件第51页浏览型号PM7350-PI的Datasheet PDF文件第52页浏览型号PM7350-PI的Datasheet PDF文件第54页浏览型号PM7350-PI的Datasheet PDF文件第55页浏览型号PM7350-PI的Datasheet PDF文件第56页浏览型号PM7350-PI的Datasheet PDF文件第57页  
RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
Ball  
Ball  
Name  
Type  
No. Function  
High Speed LVDS Links  
TRSTB  
Input  
A13 The active-low test reset (TRSTB) signal provides  
an asynchronous S/UNI-DUPLEX test access port  
reset via the IEEE P1149.1 test access port.  
TRSTB is a Schmitt triggered input with an integral  
pull-up resistor.  
Note that when not being used, TRSTB must be  
connected to the RSTB input.  
Power and Ground  
BIAS  
VDD  
Power  
Power  
A7 When tied to +5V, the BIAS input is used to bias  
the wells in the input and I/O pads so that the pads  
can tolerate 5V on their inputs without forward  
biasing internal ESD protection devices. When  
tied to +3.3V, the inputs and bi-directional inputs will  
only tolerate 3.3V level inputs.  
B3 The digital power (VDD) pins should be connected  
C5 to a well-decoupled +3.3 V DC supply.  
C13  
D10  
E2  
E14  
F3  
K1  
L1  
L4  
L9  
M7  
M12  
N3  
N13  
P6  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
41  
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