RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Ball
Name
Type
No. Function
High Speed LVDS Links
OAVALID
I/O
M9 The Output Address Valid (OAVALID) pin indicates
that the OADDR[4:0] bus is asserting a valid PHY
address for polling purposes.
As a SCI-PHY/Utopia bus master (OMASTER = 1,
OANYPHY = 0) OAVALID is an output. When this
signal is deasserted, the OADDR[4:0] bus is also
set to 0x1Fas defined by the Utopia L2 bus
standard. Therefore. Use of OAVALID is not
necessary when less than 32 PHY devices are
being polled.
As a bus slave (OMASTER = 0) OAVALID is an
input used to control the OCA output. The OCA
output is only driven when OAVALID is asserted
(sampled high in SCI-PHY/Utopia or sample low in
Any-PHY configuration) and the sampled
OADDR[4:0] value matches the OAD[4:0] bits in the
Output Address Match register. If OAVALID is
deasserted (sampled low in SCI-PHY/Utopia) or
high in Any-PHY configuration) OCA becomes high
impedance. The S/UNI-DUPLEX supports polling
in contiguous cycles if OAVALID is held high.
OCA is delayed by an additional OFCLK cycle in
Any-PHY bus configuration.
OAVALID is sampled or updated on the rising edge
of OFCLK.
This signal is only active if the SCIANY input is a
logic high.
Microprocessor Bus
CSB
Input
D8 The active-low chip select (CSB) signal is low
during S/UNI-DUPLEX register accesses.
Note that when not being used, CSB must be tied
high. If CSB is not required (i.e., registers
accesses are controlled using the RDB and WRB
signals only), CSB must be connected to an
inverted version of the RSTB input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
38
PMC [ PMC-SIERRA, INC ]
