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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
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DESCRIPTION  
The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit typically used with  
its sister device, the S/UNI-VORTEX, to implement a point-to-point serial  
backplane interconnect architecture. The primary role of the S/UNI-DUPLEX is  
to interface to up to 32 devices (typically framers or PHYs) and transfer 52-56  
byte data cells in serial format to/from a backplane. Devices interface to the  
S/UNI-DUPLEX via an 8 or 16-bit SCI-PHY/Utopia/Any-PHY bus, or optionally  
via a 16 port clock and data interface.  
Each S/UNI-DUPLEX can connect to two 100 to 200 Mb/s Low Voltage  
Differential Signal (LVDS) serial links. A microprocessor port provides access to  
internal configuration and monitoring registers. The microprocessor port may  
also be used to insert and extract cells in support of an embedded  
microprocessor communication channel.  
BUS INTERFACE:  
One of four modes can be selected:  
8 or 16 bit, Utopia L2 bus master operating at up to 33 MHz bus clock  
frequency. Also supports PMC-Sierra’s SCI-PHY bus standard which is  
compatible with Utopia L2 but allows extended length cells and supports  
an additional bus address signal in order to support 32 PHY devices  
rather than Utopia’s 31. See Table 1 for a comparison of these bus  
standards.  
16 port, 4 pin clocked serial data interface (Tx, TxClk, Rx, RxClk), with  
integrated I.432 ATM cell delineation operating at up to 52 MHz serial  
clock frequency.  
8 or 16 bit, SCI-PHY/Utopia bus slave operating at up to 52 MHz bus  
clock frequency. The slave input port presents itself as 32 addressable  
logical channels. The slave output port appears as a single addressable  
channel carrying the multiplexed traffic from up to 32 logical channels  
where each cell’s channel number can optionally be embedded in the H5  
header field (Utopia bus mode) or indicated in a cell prepend (SCI-PHY  
bus mode).  
8 or 16 bit, Any-PHY bus slave (bus protocol compatible with the PM7351  
S/UNI-VORTEX) operating at up to 52 MHz bus clock frequency. The  
slave input port presents itself as 32 addressable logical channels. The  
slave output port appears as a single addressable channel carrying the  
multiplexed traffic from up to 32 logical channels. In both directions each  
cell’s logical channel number is indicated in a cell prepend.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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