RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
5
BLOCK DIAGRAM
Although separated to improve clarity, many signals in the following diagram
share physical package pins. The use of the SCI-PHY/Any-PHY interfaces and
the clocked serial data interfaces is mutually exclusive.
SCIANY
OBUS8
OANYPHY
OMASTER
OENB
OADDR[4:0]
OAVALID
ODAT[15:0]
OPRTY
OSOC
SCI-PHY
Transmit
Master/
Receive
Slave
OSX
OFCLK
OCA
RXD1+
RXD1-
per-PHY
buffers
LTXD[15:0]
LTXC[15:0]
TXD1+
TXD1-
Time-Sliced
ATM
Transmission
Convergence
Cell
Processor
Elastic
Store
LRXD[15:0]
LRXC[15:0]
RXD2+
RXD2-
per-PHY
buffers
TXD2+
TXD2-
IBUS8
IANYPHY
IMASTER
IENB
IADDR[4:0]
IAVALID
IDAT[15:0]
IPRTY
SCI-PHY
Receive
Master/
Transmit
Slave
ISOC
ISX
IFCLK
ICA
Clock
REFCLK
A[7:0]
RDB
WRB
CSB
2 Cell
Buffer
Synthesis
Micro-
4 Cell
FIFO
Processor
Interface
TDO
TDI
TCK
TMS
TRSTB
ALE
INTB
RSTB
JTAG
Test Access
Port
to all
blocks
D[7:0]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
PMC [ PMC-SIERRA, INC ]
