RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
These registers do not have default values and must be written.
4. Clear the RESET bit of the Master Reset and Identity register (0x00) to
logic 0.
5. Manually select link 1 as the active link by writing 0x00 to the Master
Configuration register (0x01).
6. Set the IOTST bit of the Master Test register (0x80) to logic 1. This
activates the BIST test mode.
7. Start toggling the OFCLK and REFCLK or TCK and REFCLK (depending
on the SCIANY input) at up to a maximum frequency of4 MHz. Both
clocks need be phase and frequency locked.
8. After 65533 clock cycles read the following register and compare against
the expected data. Any discrepancies represent a test failure. The two
bits being compared are flags that are cleared when at least one RAM bit
location returns an incorrect value. Letting the test run indefinitely simply
causes the test sequences to be repeated.
Expected
A[7:0]
0xBE
D[7:0]
xxxx0011
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
176
PMC [ PMC-SIERRA, INC ]
