RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
DHCS:
The Disable HCS (Header Check Sequence) bit (DHCS) configures the
insertion of the HCS in the fifth byte of the cell. The value of DHCS to be
written to the channel provision RAM, in an indirect channel write operation,
must be set up in this register before triggering the write. When DHCS is
logic 0, the CRC-8 calculation over the first four bytes of the cell overwrites
the fifth byte. When DHCS is logic 1, the fifth byte of the cell passes through
unmodified. (It is still subject to scrambling.) DHCS reflects the value written
until the completion of a subsequent indirect channel read operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
168
PMC [ PMC-SIERRA, INC ]
