RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x69:
Receive Serial Indirect Channel Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PROV
HCSPASS
UNASSFLTR
IDLEPASS
DDSCR
Reserved
DDELIN
Unused
0
0
0
0
0
0
0
X
This register contains data read from the channel provision RAM of the Receive
Clocked Serial Data Interface after an indirect channel read operation or data to
be inserted into the channel provision RAM in an indirect channel write
operation.
The bits to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. The bits
reflect the value written until the completion of a subsequent indirect channel
read operation.
The reset state of the bits enables standard ATM cell processing as stipulated in
ITU-T Recommendation I.432.1.
DDELIN:
The indirect disable delineate enable bit (DDELIN) configures the TC
processor to perform cell delineation and header error detection on the
incoming data stream. When DDELIN is set to logic 0, the cell alignment is
established and maintained on the incoming data stream. When DDELIN is
set to logic 1, the RTTC does not perform any processing on the incoming
stream, but passes data through transparently.
Reserved:
This bit must be logic 0 for correct operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
159
PMC [ PMC-SIERRA, INC ]
