RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x64: Transmit High-Speed Serial Cell Counter (MSB)
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
TCELL[23]
TCELL[22]
TCELL[21]
TCELL[20]
TCELL[19]
TCELL[18]
TCELL[17]
TCELL[16]
X
X
X
X
X
X
X
X
TCELL[23:0]:
The TCELL[23:0] bits indicate the number of cells inserted into the
transmission stream during the last accumulation interval. Stuff cells inserted
into the transmission stream for rate decoupling are not counted.
A write to any one of the Transmit Cell Counter registers for a particular serial
link or a write to the Load Performance Meters (0x00) register loads the
registers with the current counter value and resets the internal 24 bit counter.
The counter should be polled at least every 30 seconds to avoid saturating.
The contents of these registers become valid within 300 ns after a transfer is
triggered by a write to any of the link-associated Transmit Cell Count registers
or to the Load Performance Meters (0x00) register, and remain valid until
another transfer is triggered.
The count saturates at all ones.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
156
PMC [ PMC-SIERRA, INC ]
