RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x68: Receive Serial Indirect Channel Select
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R/W
R/W
CBUSY
CRWB
X
0
0
X
0
0
0
0
DRHCSE
Unused
CHAN[3]
CHAN[2]
CHAN[1]
CHAN[0]
R/W
R/W
R/W
R/W
This register provides the channel number used to access the channel provision
RAM of the receive Clocked Serial Data Interface. Writing to this register triggers
an indirect channel register access.
CHAN[3:0]:
The indirect channel number bits (CHAN[3:0]) indicate the channel to be
configured or interrogated in the indirect access.
DRHCSE:
Disable Reset of the HCS Error Count (DRHCSE) disables automatic reset of
the HCS Error Counter (HCSERR). When the bit is set to logic 0, automatic
reset of the HCS Error Counter is enabled. If an indirect read is initiated (i.e.,
CRWB written with logic 1) with DRHCSE logic 0, the HCS Error Counter is
reset to zero upon completion of the indirect read. When the DRHCSE bit is
set to logic 1, automatic reset of the HCS Error Counter is disabled.
CRWB:
The channel indirect access control bit (CRWB) selects between a configure
(write) or interrogate (read) access to the channel provision RAM. Writing a
logic 0 to CRWB triggers an indirect write operation. Data to be written is
taken from the Receive Serial Indirect Channel Data registers. Writing a logic
1 to CRWB triggers an indirect read operation. The data read can be found
in the Receive Serial Indirect Channel Data registers.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
157
PMC [ PMC-SIERRA, INC ]
