RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
CBUSY:
The indirect access status bit (CBUSY) reports the progress of an indirect
access. CBUSY is set to logic 1 when a write to the Receive Serial Indirect
Channel Select register triggers an indirect access and will remain logic 1
until the access is complete. This register should be polled to determine
when data from an indirect read operation is available in the Receive Serial
Indirect Channel Data registers or to determine when a new indirect write
operation may commence. The CBUSY is not expected to remain at logic 1
for more than two REFCLK cycles.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
158
PMC [ PMC-SIERRA, INC ]
