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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
Register 0x0E: SCI-PHY/Any-PHY Input Interrupt Enables  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
Unused  
Unused  
Unused  
Unused  
X
X
X
X
X
0
R/W  
R/W  
R/W  
PHYCELLE  
CELLXFERRE  
PARERRE  
0
0
The Master Interrupt Enable bit of the Master Configuration register must also be  
logic 1 for these enables to take effect.  
PHYCELLE:  
The PHYCELLE bit enables the generation of an interrupt when a physical  
layer cell is transferred over the SCI-PHY/Any-PHY input port. When  
PHYCELLE is set to logic 1, the interrupt is enabled. Physical layer cells are  
defined in the I.361 standard as IDLE, unassigned and reserved cells (i.e.  
cells with a VPI = 0 and VCI = 0). These cells should be filtered out by the  
PHY device and would not normally be sent to the S/UNI-DUPLEX.  
CELLXFERRE:  
The CELLXFERRE bit enables the generation of an interrupt upon an invalid  
start of cell sequence. When CELLXFERRE is set to logic 1, the interrupt is  
enabled.  
PARERRE:  
The PARRERRE bit enables the generation of an interrupt on an input cell  
parity error. When PARRERE is set to logic 1, the interrupt is enabled.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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