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PM7350-PI 参数 Datasheet PDF下载

PM7350-PI图片预览
型号: PM7350-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行链路物理层复用器 [DUAL SERIAL LINK PHY MULTIPLEXER]
分类和应用: 复用器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 241 页 / 1939 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI-DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 5  
DUAL SERIAL LINK PHY MULTIPLEXER  
Register 0x0F: SCI-PHY/Any-PHY Input Interrupt Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
Unused  
Unused  
Unused  
Unused  
X
X
X
X
X
0
R
R
R
PHYCELLI  
CELLXFERRI  
PARERRI  
0
0
PHYCELLI:  
The PHYCELLI bit is set to logic 1 when a physical cell is transferred over the  
SCI-PHY/Any-PHY input port. This bit is reset immediately after a read to this  
register.  
CELLXFERRI:  
The CELLXFERRI bit is set to logic 1 when an invalid start of cell sequence is  
detected, i.e. ISOC or ISX is asserted when not expected at the SCI-  
PHY/Any-PHY input port. This bit is reset immediately after a read to this  
register.  
The same event that asserts this bit may also result in a corrupted cell being  
transmitted on a high-speed serial link.  
PARERRI:  
The PARERRI bit is set to logic 1 when a parity error occurs while receiving a  
cell at the SCI-PHY/Any-PHY input port. This bit is reset immediately after a  
read to this register.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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