RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0F: SCI-PHY/Any-PHY Input Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
X
X
X
X
X
0
R
R
R
PHYCELLI
CELLXFERRI
PARERRI
0
0
PHYCELLI:
The PHYCELLI bit is set to logic 1 when a physical cell is transferred over the
SCI-PHY/Any-PHY input port. This bit is reset immediately after a read to this
register.
CELLXFERRI:
The CELLXFERRI bit is set to logic 1 when an invalid start of cell sequence is
detected, i.e. ISOC or ISX is asserted when not expected at the SCI-
PHY/Any-PHY input port. This bit is reset immediately after a read to this
register.
The same event that asserts this bit may also result in a corrupted cell being
transmitted on a high-speed serial link.
PARERRI:
The PARERRI bit is set to logic 1 when a parity error occurs while receiving a
cell at the SCI-PHY/Any-PHY input port. This bit is reset immediately after a
read to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
108
PMC [ PMC-SIERRA, INC ]
