RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0D: SCI-PHY/Any-PHY Input Configuration 2
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
ENFLTR
X
0
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NNI
PHYDEV[4]
PHYDEV[3]
PHYDEV[2]
PHYDEV[1]
PHYDEV[0]
PHYDEV[4:0]:
The PHYDEV[4:0] bits are used to define the polling range of the SCI-
PHY/Any-PHY input port when configured as a bus master (IMASTER is set
to logic 1) The number of PHY devices to be polled is configured as follows:
PHYDEV[4:0]
00000
00001
00010
00011
:
Description
Poll all 32 devices
Poll PHY#1 thru PHY#2
Poll PHY#1 thru PHY#3
Poll PHY#1 thru PHY#4
:
11110
11111
Poll PHY#1 thru PHY#31
Poll all 32 PHY devices
Setting PHYDEV[4:0] to poll more PHY devices than actually connected to
the SCI-PHY/Any-PHY input port may result in loss of cell throughput due to
longer than necessary polling cycles.
NNI:
The NNI bit selects whether the UNI or NNI cell header format is used when
determining whether a cell is unassigned or reserved for the Physical Layer.
When set to logic 1 (default), the NNI format is used. When set to logic 0, the
UNI format is used, i.e. the 4 most significant bits of Byte 1 of the cell header
are ignored.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
105
PMC [ PMC-SIERRA, INC ]
