RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0C: SCI-PHY/Any-PHY Input Configuration 1
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
H5UDF
Unused
Unused
Reserved
PRELEN[1]
PRELEN[0]
Unused
1
X
X
0
0
0
X
0
R/W
R/W
R/W
R/W
PTYP
PTYP:
The Parity Type (PTYP) bit selects even or odd parity for the IPRTY input of
the SCI-PHY/Any-PHY input port. When set to logic 1, IPRTY is the even
parity bit for IDAT[15:0] if IBUS8 input is low or for IDAT[7:0] if IBUS8 input is
high. When set to logic 0, IPRTY is the odd parity bit for IDAT[15:0] if IBUS8
input is low or for IDAT[7:0] if IBUS8 input is high.
PRELEN[1:0]:
The Prepend Length (PRELEN[1:0]) bits determine the number of words
prepended to each cell received on the SCI-PHY/Any-PHY input port.
When IBUS8 is a logic 1, the binary PRELEN[1:0] value indicates whether the
optional “Word 1” and “Word 2” illustrated in Fig. 6 are included in the data
structure expected on IDAT[7:0]. The possible values are:
PRELEN[1:0]
Description
00
01
10
no prepended word
“Word 1” only is included
“Word 1:” and “Word 2” are included
When IBUS8 is a logic 0, only PRELEN[0] is used. When PRELEN[0] is logic
1, the optional “Word 1” illustrated in Fig. 7 is included in the data structure
expected on IDAT[15:0].
Reserved:
This bit must be logic 0 for correct operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
103
PMC [ PMC-SIERRA, INC ]
