RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0A: Output Address Match
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
OCAEN
OAD[4]
OAD[3]
OAD[2]
OAD[1]
OAD[0]
X
X
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
OAD[4:0]
The OAD[4:0] bits are used in the selection of the output port of the SCI-
PHY/Any-PHY interface for polling and cell transfer. Polling occurs when the
OAVALID input is sampled high and the sampled OADDR[4:0] inputs match
the OAD[4:0] bits. A transfer is enacted if the value of the OADDR[4:0] inputs
equals the OAD[4:0] bits when OENB is last sampled high.
OCAEN:
The OCAEN bit controls whether the OCA output is driven in response to
polling when the SCI-PHY/Any-PHY interface output port is operated in bus
slave mode (OMASTER set to logic 0). If OCAEN is set to logic 0, the OCA
output pin stays unconditionally high impedance. If OCAEN is set to logic 1,
OCA drives upon sampling a logic 1 on OAVALID while OADDR[4:0] value is
equal to OAD[4:0] bits of this register. OCAEN should only be set to logic 1
after the aforementioned register bits have been initialized.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
100
PMC [ PMC-SIERRA, INC ]
