RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
processed – user cells are discarded. Both links discard stuff cells after
extracting the system overhead. The active link uses all fields of the system
overhead on each cell. The inactive link monitors the PHYID (only to identify
control channel cells), the ACTIVE, BOC, and TREF fields. Both links monitor for
loss of signal and loss of cell delineation conditions. Cells received with an
incorrect Header Check Sequence (HCS) (due to bit errors during transmission)
are counted and discarded. The system overhead fields of errored cells are
ignored.
User and control channel cells received from the high-speed serial link are
temporarily stored in a shallow buffer partitioned into a separate FIFO for each
logical channel. As discussed below, cells are read out of this buffer under the
control of the parallel bus, the clocked serial data, or the microprocessor
interface. The buffer is logically partitioned into a FIFO for each logical channel.
Each FIFO has an associated flow control bit (CA for user cells, UPCA for the
control channels) embedded within the prepended bytes in the upstream high-
speed serial link.
The 34 (32 PHYs + 2 control channels) channel FIFOs are four cells deep.
When a FIFO contains less than two cells, the corresponding flow control bit is
set to allow cell transmission. Upon the beginning of the write of a cell which will
place the second cell in the FIFO, the flow control bit becomes a zero until only
one cell remains in the FIFO. The far end device (either another S/UNI-DUPLEX
or a S/UNI-VORTEX) will only resume sending cells to that PHY or control
channel when its flow control bit has been set to a one. Since the flow control bit
is encoded into the next upstream cell (either a user data cell or a filler cell) there
will be some latency between the setting and clearing of the flow control bit and
the corresponding action by the far-end device. However, since the far-end
buffer is four cells deep no overflow condition will occur.
The process of reading cells out of the per channel FIFOs and placing them on
the parallel bus is flow controlled by the bus polling protocol, as discussed in
Section 9.1. When operating with the clocked serial data interface, cells are read
from the FIFO at a rate determined by the transmit clock provided to the S/UNI-
DUPLEX by the modem. If the FIFO contains less than one complete cell when
the previous cell has been serialized then an idle cell will be emitted. Idle cell
generation has no impact of the channel’s FIFO.
See Section 9.7.1 for a description of how the two control channel interfaces are
presented to the microprocessor port.
9.4.2 LVDS Transmit Traffic Flow Control
In the LVDS transmit direction, the primary task of the S/UNI-DUPLEX is accept
cells from the parallel bus, clocked serial interfaces, or microprocessor port
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PMC [ PMC-SIERRA, INC ]
