RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
register (0x5E) to be four cells deep as per the I.432 specification. If flow control
asserted by the far-end device prevents cells from a particular serial data
interface from being read, the corresponding FIFO will begin to fill. In general,
proper system engineering should ensure that the far-end is able to keep up, but
should flow control continue to be asserted by the far-end an overflow condition
could occur. Overflow results in an optional interrupt being raised, an error status
register being set, and subsequently received cells being discarded until FIFO
space is available.
Regardless of whether configured a bus master, bus slave, or clocked serial data
device, the S/UNI-DUPLEX monitors the per-channel FIFOs and performs round
robin scheduling of cells onto the transmit LVDS links. The control channel FIFO
is given equal priority to the PHYs.
The device attached to the far-end of the LVDS link is typically a S/UNI-VORTEX
(see Fig. 1) or a S/UNI-DUPLEX (see Fig. 4 and Fig. 5). Although the S/UNI-
DUPLEX only implements one form of transmit flow control, to help understand
the end-to-end flow control we will discuss the two situations separately.
Case #1: the far-end device is a S/UNI-VORTEX
The S/UNI-VORTEX is a parallel bus slave with a single receive buffer for each
of its eight LVDS links. It uses a weighted round robin polling of these buffers
and schedules the received cells onto the parallel bus under the control of the
bus master. The S/UNI-VORTEX’s eight LVDS links running at 200 Mb/s can
provide aggregate traffic bursts that exceed the capacity of a 800 Mb/s parallel
bus. Also, link polling weights may be set such that one or more links receive
relatively less of the aggregate bus bandwidth. Therefore, it is quite likely that
congestion will sometimes occur at the S/UNI-VORTEX’s LVDS receive buffers.
Since all traffic received on the eight LVDS links is heading to the S/UNI-
VORTEX’s parallel bus there was no need to partition this FIFO into individual
channels. Therefore the S/UNI-VORTEX implements flow control on each of its
LVDS links in a binary fashion – all 32 logical channels are enabled or all
channels are disabled. The S/UNI-VORTEX may or may not treat the
microprocessor control channel independently from the user channels depending
on how it is configured. If it is programmed to route control channel cells out over
the parallel bus then the control channel flow control is identical to the 32 user
channels. If the control channel is being routed to the microprocessor port then
the control channel flow control is independent from the user channels.
When the S/UNI-VORTEX’s LVDS receiver cell buffer becomes congested the
S/UNI-VORTEX will immediately clear the CA bits and possibly the UPCA fields
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
76
PMC [ PMC-SIERRA, INC ]
