RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
The receiver can be enabled to declare a received code valid if it has been
observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit
in the Bit Oriented Code Receiver Enable register. Unless fast declaration is
necessary, it is recommended that the AVC bit be set to logic 0 to improve bit
error tolerance. Valid BOC are indicated through the RXD1 Bit Oriented Code
Status and RXD2 Bit Oriented Code Status registers. The BOC bits are set to all
ones (111111) if no valid code has been detected. A maskable interrupt is
generated to signal when a detected code has been validated, or optionally,
when a valid code goes away (i.e. the BOC bits go to all ones).
When the receiver is out of cell delineation (OCD), the BOC detection is disabled
and the corresponding RXD1 or RXD2 Bit Oriented Code Status register will
produce all ones (111111). .
The valid codes are provided in Table 17. The Reserved codes anticipate future
enhanced feature set devices and should not be used. The User Defined codes
may be used without restriction. Regardless of definition, all 63 codes may be
validated and read by a microprocessor. Only four codes result in autonomous
action: loopback activate, loopback deactivate, reset output activate and reset
output deactivate.
Note that processing of the metallic loopback activate code is handled as a
special case. The RXD1+/-, RXD2+/- data is looped back onto TXD1+/-, TXD2+/-
respectively at the end of the reception of the loopback activate code on the
corresponding high-speed serial link rather than when the code is first validated.
For the loopback to be enabled the loopback code must be first validated
(received 8 out of 10 times at least once) and then invalidated, typically by
reception of another code. The loopback is not enable upon initial validation of
the loopback activate code because the looped back signal, which still contains
the original loopback activate command, would cause the far-end receiver to go
into metallic loopback, thereby forming an undesirable closed loop condition! The
loopback is cleared immediately upon the validation of the loopback deactivate
code, assuming the corresponding MLB register bit of the Serial Links
Maintenance register is logic 0.
To produce a loopback at the far end, program the desired TXD1 Bit Oriented
Code or TXD2 Bit Oriented Code register with the loopback activate code for at
least 1 ms and then revert to another (typically idle) code. Upon termination of
the loopback activate code, the data transmitted on TXD1+/- or TXD2+/- is
expected to be received verbatim on the RXD1+/- or RXD2+/- inputs. When
transmitting a loopback activate code on a high-speed serial link, it is
recommended the corresponding RDIDIS1 or RDIDIS2 register bit be set to logic
1, or else a loss-of-signal or loss-of-cell-delineation event would cause a
premature loopback due to a pre-emptive Remote Defect Indication (RDI) code
being sent.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
70
PMC [ PMC-SIERRA, INC ]
